The present invention relates to a state tracer system which allows tracing data before the stop condition of a tracer memory is met to be collected.
In a general tracer memory as shown in FIG. 1, when it is in the running condition, an address 43 of a RAM 31 is counted up by an address counter comprising an arithmetic operation circuit 33 and a register 34. Meanwhile, write data 40 is entered to the RAM 31 via a register 30. Further, since the stop condition of a write pulse 48 is not met, it is entered to the RAM 31. Therefore, data 40 is written into the RAM 31 for each clock.
In the tracer memory mentioned as above, if a stop signal 51 is entered to a stop condition circuit 35 as some error occurs, then the stop condition is met, and the count up of address 43 is suppressed, while a write pulse 47 fed to the RAM 31 via an AND 36 is suppressed. In this stop condition, the address 42 is entered to the arithmetic operation circuit 33 so that data 50 are read out of the RAM 31 via the register 32. If the address 42 is counted up starting from zero (0), then the data present prior to the time when the stop condition is met is sequentially read out.
In such a tracer memory, the history of the trace data which is obtained at the time the stop condition is met has been limited to ones which can be traced back to several micorseconds before because the storage capacity of the RAM is limited, which has made it impossible to collect those traced back to several tens to hundreds of microseconds before the time the stop condition is met.